Design-Reuse

Andes Technology Announces RISC-V Single-core and Multicore Processors with DSP Instruction Set

Hsinchu, Taiwan, Mar. 12, 2019 – At the RISC-V Workshop Taiwan cohosted by Andes Technology today, Andes proudly announces the debut of its 32-bit A25MP and 64-bit AX25MP RISC-V multicore processors.
Design-Reuse

DSP Group and Endeavor Intertech Announce High Performance, Certified Accurate Instruction Set Simulation for TeakDSPCore

SAN JOSE, Calif., IP 2000 System-on-Chip Conference, March 20 -- Endeavor Intertech Corporation and DSP Group, Inc. announced today the launching of IPSim for Teak(TM), the new Certified Accurate ...
Electronic Design

Processor Runs Four Instruction Sets

Most processors run a single instruction set. But the ARM1026EJ-S implements four in hardware, including 32-bit ARM instructions, 16-bit ARM Thumb instructions, ARM DSP instructions, and Java ...
Electronic Design

Instruction-Set Extensions Let CPU Accelerate Key Operations

The S5000 software-configurable processor family combines the flexibility of the compilable Tensilica Xtensa RISC processor core and the programmable Stretch instruction-set extension fabric (ISEF) to ...
New Electronics

First working silicon of a DSP with embedded FPGA

Flex Logix Technologies, a supplier of reconfigurable computing solutions, architecture and software, and CEVA, a licensor of wireless, sensing and integrated IP solutions, have announced the first ...
Semiconductor Engineering

High-Performance DSP And Control Processing For Complex 5G Requirements

In the early 2000s, digital signal processors (DSP) were simple in architecture and limited in performance, but complex in programming. However, they evolved to meet of the increased performance ...