EDN

Translator bridges Vera code to SystemVerilog 3.1

Santa Cruz, Calif. – Startup VeriEZ Solutions Inc. has announced fourth-quarter availability of EZTranslate, which will serve as a bridge between Synopsys Inc.'s Vera-based verification environments ...
Semiconductor Engineering

Find Bugs Early: On-The-Fly Code Correction For Design And Verification Productivity

The key rule for chip design and verification is that bugs must be found and fixed as early in the development process as possible. It is often said that catching a bug at each successive project ...
Design-Reuse

How to raise the RTL abstraction level and design conciseness with SystemVerilog - Part 2

As discussed in Part 1, this article proposes four steps to raise the abstraction level of current Verilog HDL designs and provide a phase wise approach to migrate to SystemVerilog. Enhance ...
EDN

An overview of SystemVerilog 3.1

SystemVerilog is an extensive set of enhancements to the IEEE 1364 Verilog-2001 standard. These enhancements provide powerful new capabilities for modeling hardware at the RTL and system level, along ...
Design-Reuse

AMIQ EDA Introduces Duplicate Code Detection in Its Verissimo SystemVerilog Testbench Linter

AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development and analysis ...
Electronic Design

Find the Fastest Route to Portable Stimulus Tests with SystemVerilog

The new Accellera Portable Stimulus Specification language offers advantages such as portability across verification levels and greater test-creation productivity. The Portable Stimulus Specification ...